1. Field of the Invention
This invention relates to a method for fabricating complementary FET structures, and more particularly to a method for implanting self-aligned n.sup.+ and p.sup.+ source and drains using only one lithography mask.
2. Description of the Prior Art
Various fabrication techniques for making complementary integrated circuits are known in the prior art. These techniques employ variations and combinations of doping implantation, masking and similar processes for defining and creating the device regions of the circuit.
Typical prior art references are as follows.
U.S. Pat. No. 3,759,763 issued Sept. 18, 1973 to Wang entitled METHOD OF PRODUCING LOW THRESHOLD COMPLEMENTARY INSULATED GATE FIELD EFFECT DEVICES describes a fabrication process for C-IGFET's including diffusion and etching steps of general interest. U.S. Pat. No. 4,027,380 issued June 7, 1977 to Deal et al and entitled COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTOR STRUCTURE AND PROCESS FOR FABRICATING THE STRUCTURE describes a process for fabricating a complementary insulated gate field effect transistor structure having complementary p-channel and n-channel devices in the same semiconductor substrate wherein the process for fabricating the structure incorporates oxide isolation of the active device regions, counterdoping of the p-well with impurities of opposite type to obtain a composite doping profile, reduction of Q.sub.33 in the isolation oxide, doping of the gate and field oxides with a chlorine species and phosphorus doping of the polycrystalline silicon gates.
U.S. Pat. No. 4,244,752 issued Jan. 13, 1981 to Henderson, Sr. et al entitled SINGLE MASK METHOD OF FABRICATING COMPLEMENTARY INTEGRATED CIRCUITS describes a method of fabricating an integrated circuit having a plurality of different devices, which method employs a single mask to define the active areas of all such devices. A silicon oxide-silicon nitride layer is formed on the surface of a silicon wafer so as to define the location of subsequent oxide insulating layers which in turn actually define all the active areas of the circuit. Respective active areas for the different devices can then be formed by selective ion implantation. U.S. Pat. No. 4,144,101 issued Mar. 13, 1979 to Rideout and entitled PROCESS FOR PROVIDING SELF-ALIGNED DOPING REGIONS BY ION-IMPLANTATION AND LIFT-OFF is of interest in that it describes a technique wherein an undercut resist masking pattern is used as an ion implantation mask. More particularly, a process is described for providing ion-implanted regions in a substrate such as silicon beneath an existing layer such as silicon dioxide and being self-aligned to subsequently fabricated regions of said layer which includes providing a resist masking pattern above the existing layer wherein the resist masking pattern is undercut; ion-implanting impurities such as boron ions through the layer but not through the resist and portions of the layer beneath the resist; and depositing a layer of lift-off material such as aluminum on the existing layer and on the resist. This reference relates to a multiple masking process.
The described prior art references do not relate to a single mask process wherein a resist mask defines a first implant and then serves as a reverse mask for a second implant.